Specifications

CMOS technology0.25μm
Pixel size55μm x 55μm
Pixel matrix256 x 256
DesignCERN
Positive and negative signal polarity
Leakage current-10nA to +20nA
Time to peak100ns
Noise100 e- rms
Threshold variation (after tuning)35 e- rms
Minimum operating treshold700 e-
1 counter / shift register14 bits (stops at 11810 counts)
Periphery
  • 13 8-bit DACs to set voltages in the chip
  • Serial raedout 1-bit LVDS
  • Parallel readout 32-bit CMOS
  • Readout time in serial mode (100 MHz clock): 9μs
  • Readout time in parallel mode (100 MHz clock): 266μs
Total analog power consumption (nominal conditions)440mW
Total digital power consumption (@100MHz)450mW
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