Specifications

Signal polarity	Positive and negative
Leakage current	-10nA to +20nA
Time to peak	120ns
Noise	80 e- (SPM) 175 e- (CSM)
Threshold variation (after tuning)	35 e- rms
Minimum operating treshold	700 e-

Configurable counter depths	2 x 1-bit 2 x 4-bit 2 x 12-bit 1 x 24-bit
25 DACs (10 9-bit and 15 8-bit) to set voltages in the chip
LVDS drivers and receivers (configuration of the chip in serial mode)
Parallel data port configurable to 1, 2, 4 or 8 LVDS lines
Readout time 8 parallel LVDS lines (200 MHz clock, 12 bit counters)	491μs
Continuous Read/Write	YES
Hit rate 28 – 826 Mcounts/mm²/s depending on configuration
Total analog power consumption (nominal conditions)	440mW
Total digital power consumption (@100MHz)	450mW