| General | |
|---|---|
| CMOS technology | 0.25μm |
| Pixel size | 55μm x 55μm |
| Pixel matrix | 256 x 256 |
| Design | CERN |
| Analog front end (pixel cell) | |
|---|---|
| Positive and negative signal polarity | |
| Leakage current | -10nA to +20nA |
| Time to peak | 100ns |
| Noise | 100 e- rms |
| Threshold variation (after tuning) | 35 e- rms |
| Minimum operating treshold | 700 e- |
| Digital part (pixel cell + periphery) | |
|---|---|
| 1 counter / shift register | 14 bits (stops at 11810 counts) |
| Periphery |
13 8-bit DACs to set voltages in the chip Serial raedout 1-bit LVDS Parallel readout 32-bit CMOS Readout time in serial mode (100 MHz clock): 9μs Readout time in parallel mode (100 MHz clock): 266μs |
| Total analog power consumption (nominal conditions) | 440mW |
| Total digital power consumption (@100MHz) | 450mW |